Certain types of circuits that perform mathematical operations may require multiple adder circuits, such as carry-propagate or ripple-carry adders, which are inefficient. For example, in a symmetrical finite impulse response (FIR) filter, inputs may be added prior to being multiplied, which reduces the number of multipliers. However, that addition requires a pre-adder, and then the multiplication itself may include a compressor followed by another adder. The provision of multiple adders consumes a substantial amount of integrated circuit device area, and is of particular concern in programmable logic devices such as field-programmable gate arrays (FPGAs).
Moreover, large multiplication problems, such as those encountered in FIR filters, may require large compressor trees. The size of the compressor tree can be reduced by increasing the radix of the multiplier, but that in turn may require non-power-of-two manipulations of the inputs, which cannot be performed by simple shifting (as can be done for power-of-two manipulations), and may introduce the need for still more adders.